RQC Seminar

106th RQC Seminar

• Speaker

  Mr. Siddhant Singh
  ( QuTech, Quantum Internet Division, Applied Physics, TU Delft, the Netherlands )

• Date

  16:00-17:00, February 2, 2024 (Friday)

• Venue

  Hybrid(ZOOM・ Wako Main Research 4F 445-457 Seminar room C01）

• Title

  MODULAR ARCHITECTURES AND ENTANGLEMENT SCHEMES FOR ERROR-CORRECTED DISTRIBUTED QUANTUM COMPUTING

• Inquiries

  rqc_info[at]ml.riken.jp

Abstract
This research presents modular architectures inspired by surface codes designed explicitly for distributed quantum computation (DQC) applications. The generation of remote entanglement assumes a pivotal role in these quantum error correction (QEC) architectures, as distributed stabilizer measurements necessitate GHZ states. We present the known weight-4 surface code architecture and propose the new weight-3 architecture, which both rely on GHZ states with corresponding weights arising due to the choice of node topology. To achieve remote entanglement generation, we explore established emission-based schemes that involve creating and fusing Bell pairs among nodes to realise the desired GHZ states via the emission of photons from the atomic qubit and their interference. In addition, we propose three novel entanglement generation schemes. The first is a reflection scheme, which uses light scattering off one-sided cavities to generate GHZ states via the interference of early and late time-bin photonic qubits. The second (third) scheme is a cavity (waveguide) GHZ carving scheme, where atomic qubits are strongly coupled to a two-sided cavity (waveguide), enabling GHZ state creation through photon transmission through the cavity (waveguide) and interference of photonic qubits in different optical routes of the setup. Each scheme is investigated for both coherent and single photon sources. We optimise the success probability and GHZ state fidelity to achieve the highest code error threshold. Subsequently, we evaluate the error-correction thresholds associated with these schemes, specifically targeting hardware implementations, by including characteristic noise sources, including entanglement generation noise, qubit decoherence, imperfect gate operations, circulator loss, line broadening, fibre and cavity losses, dark counts, as well as non-ideal photon detection. When combined with a specific architecture, we identify the key parameters that lead to optimal performance. We further investigate the potential improvements in near-future hardware setups by varying these parameters. Our findings demonstrate significant advancements in DQC surface code thresholds, with selected proposals approaching the thresholds of non-distributed implementations for near-future parameters. To compare the architectures, we comprehensively assess DQC code thresholds, QEC cycle times, logical success rates, and physical hardware feasibility. These evaluations provide valuable insights to facilitate the selection of the most suitable architecture for a given physical implementation of DQC, thereby aiding initial experiments in identifying key hardware parameters and making informed decisions to optimise system performance.