RQC Seminar

94th RQC Seminar

  • Speaker

    Dr. Takahiro Tsunoda
    ( Yale University, USA )

  • Date

    14:30-15:30, November 9, 2023 (Thursday)

  • Venue

    Hybrid(ZOOM・ Room S507 at Wako Chem. & Mat.Phys. Bldg.)

  • Title

    Error-detectable bosonic entangling gates for fault-tolerant quantum computing

  • Inquiries

    rqc_info[at]ml.riken.jp

Abstract
Bosonic quantum error correction (QEC) has proven to be a successful approach for extending the coherence of quantum memories [2, 3, 4]. However, to execute deep quantum circuits or embed bosonic logical qubits in higher-layer QEC codes such as the surface code, high-fidelity entangling gates between encoded qubits are necessary.
A significant challenge in engineering entangling gates is reducing the physical error rate at the hardware level. Major efforts are being directed at understanding the physical limits in various platforms, either by improving the coherence of the quantum elements or reducing the time required for a gate since t_gate/T_coh often sets the limit for gate fidelities. Significant improvements in fidelity are needed either to allow practical NISQ algorithms or to enable scalable error correction.
In this talk, we introduce a gate construction that enables error detection in bosonic entangling gates, where errors during operations can be directly detected in the quantum hardware [1]. Error-detected gates are predicted to have orders of magnitude lower gate infidelities, which scale as (t_gate/T_coh)^2 when we detect jump errors to first order. When a gate fails, we can deal with this either by simple post-selection for NISQ algorithms or by entirely correcting this error by treating it as an erasure within a larger error-correcting code [5, 6, 7].
Remarkably, the protocol only requires a standard setup in the circuit QED where bosonic qubits are stored in microwave cavity modes and controlled via an ancilla transmon which is dispersively coupled to only one of the bosonic modes. Control can then be extended to both bosonic qubits by also engineering a parametric beamsplitter interaction, which exchanges photons between the two bosonic modes [8, 9, 10].
The proposed construction detects all dominant error mechanisms in the circuit QED hardware, including photon loss in the bosonic modes, ancilla dephasing, and ancilla decay errors. As such, error-detected gate infidelities scale only quadratically with coherence times, as (t_gate/T_coh)^2, which we verify with extensive numerical simulations. This scheme can be immediately applied with current hardware [8, 9, 10], improving fidelity significantly and taking today’s typical 99% entangling gate fidelities to 99.99% when no errors are detected. This approach shows great promise for improving NISQ computations and opening a different and more efficient path to realizing fault-tolerant quantum computing via erasure qubits.

[1] Tsunoda, Teoh et al., PRX Quantum 4, 020354 (2023)
[2] Ofek et al., Nature 536, 441-445 (2016)
[3] Sivak et al., Nature 616, 50-55 (2023)
[4] Sun et al., Nature 616, 56-60 (2023)
[5] Gao et al., Nature 566, 509-512 (2019)
[6] Chapman et al., PRX Quantum 4, 020355 (2023)
[7] Lu et al., arxiv:2303.00959 [quant-ph]
[8] Thompson et al., Nature Communications 13, 4657 (2022)
[9] Teoh et al., arxiv:2212.12077 [quant-ph]
[10] Kubica et al., arxiv:2208.05461 [quant-ph]


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